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ISO 26262 Part 5 – Hardware Overview (Semiconductors)

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Seminar Content

This 5 day seminar is intended to enable participants to:

  • Identify Product Development at the Hardware Level in light of ISO 26262 part 11
  • Understand the Requirements of ISO 26262 Parts 4 and 6 and how they affect Hardware development
  • Describe Hardware Evaluation requirements and Requirements Verification
  • Describe the impact on Semiconductor development
  • Describe the different types of Hardware Metrics
    • Implement the development of Structural Metrics
    • Describe the development of Safety Reliability Metrics
  • Understand the impact of ISO 26262 Parts 4 and 6 on hardware development

Who Should Attend

This seminar is designed for E/E & HW project managers, HW developers, Hardware Design Engineers and Functional Safety Engineers.

Recommended Training and/or Experience

Attendees should have a working knowledge of their organization’s New Product Development Process.

Seminar Materials

Each participant will receive seminar manual.

Seminar Outline

  • Introduction and Overview to ISO 26262
  • Management of Functional Safety (Part 2)
    • Three clauses
      • Overall management
      • Project management
      • After Release management
    • Impact Analysis
    • Confirmation measures
    • Breakout: – Safety Case
  • Safety Element Out of Context
  • Concept Phase (Part 3)
    • Breakout: – Item Definition
    • Breakout: – HARA and Safety Goals
  • Safety Requirements
    • Breakout: – Functional Safety Requirements / Concept
  • System Level Development I (Part 4) - overview
    • ASIL and Safety Oriented Analysis
    • ASIL Decomposition Case Study
    • Safety Analyses in ISO 26262
    • HSI development
    • The V model; Planning for V&V testing
  • Hardware Level Development (Part 5)
  • Hardware Safety Requirements
    • How to consider semiconductor components
      • Semiconductor component development
    • Case Study
  • Hardware Design
    • adapting a semiconductor component safety analysis to system level
    • Intellectual Property (IP)
    • Specific semiconductor technologies and use cases
      • Digital components and memories
      • Analogue/mixed signal components
      • Programmable logic devices
      • Multi-core components
      • Sensors and transducers
  • Analysis of HW Design
    • Qualitative and quantitative analysis of digital component.
    • Notes about safety analysis
    • Implications for multi-core components
    • Safety analysis for sensors and transducers.
  • Overview of Hardware Metrics
    • About hardware faults, errors and failure modes
    • Base failure rate for semiconductors
    • Semiconductor dependent failure analysis
  • SPF and LF Metrics
  • Development of structural metrics
    • FIT Rates
    • Breakout: -- FMEDA
    • Breakout: -- Fault Tree Analysis
  • Evaluation of Safety Goal Violations Due to Random HW Failures
    • Development of Safety Reliability Metrics
  • Fault Classes
  • Diagnostic Coverage Analysis part 5 annex A
  • Dependent Failure Analysis part 5 annex B
  • Quantitative Analysis part 5 annex C, D , E
    • Fault Classes
    • Case Study (continued)
  • Support Activities (Part 8)
    • Evaluation of hardware elements
    • Proven Use in Argumentation
    • Interfaces within distributed developments
  • Clarification on hardware integration and verification
  • Software Level Development (Part 6) - overview
    • Interface with HW in part 11
    • Qualification of Software Components
  • System Level Development II (Part 4 - overview continued)
  • Part 7 – Production and Operation
  • Qualification of Software Tools
  • Summary

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